1. Field of the Invention
This invention relates to a semiconductor process, and more particularly, to a method of fabricating a dual damascene structure.
2. Description of Related Art
As the integration of the integrated circuit (IC) increases, the number of interconnection is consequently increased. Therefore, more than two layers of metal layer become necessary design for most integrated circuit. As the integration of the integrated circuit continually increases, the difficulties of forming metal inter-connections with high yield and reliability increase as well. Dual damascene technique is therefore proposed. Dual damascene technique satisfies the requirement of high yield and reliability by the process steps, including etching metal interconnection trenches in the dielectric layer and then filling metal into the trenches. As a result, dual damascene technique becomes the best choice of sub-quarter micron interconnection fabrication.
FIG. 1A to FIG. 1C illustrates the fabrication process of a conventional dual damascene. Referring to FIG. 1A, on a substrate 10, a conductive layer 14 is formed. The conductive layer 14 is used for coupling the substrate 10 to other desired structures (not shown). An inter-metal-dielectric layer 12 is also formed to prevent undesired close or coupling of the conductive layer 14 and other desired structure at undesired points.
Next, an oxide layer 16 is formed to cover the conductive layer 14 by low-pressure chemical vapor deposition (LPCVD). A mask layer 18 is then formed to cover the oxide layer 16 by LPCVD. The mask layer 18 is a silicon nitride layer usually. Using the same LPCVD, an oxide layer 20 is formed to cover the mask layer 18. Next, a photoresist layer 21 is coated to define the oxide layer 20 to expose a portion of the oxide layer 20. The exposed portion of the oxide layer 20 is corresponding to the conductive layer 14.
Referring to FIG. 1B, the exposed oxide layer 20 is etched, using conventional photolithography and etching. The etching process is continued until the mask layer 18 is etched through to form an opening 22 exposing the oxide layer 16. The photoresist layer 21 is then removed, by oxide plasma. Next, a second photoresist layer 24 is coated to further define the oxide layer 20 so that the opening 22 and a portion of the oxide layer 20, including the oxide layer at two sides of the opening 22, are exposed.
Referring to FIG. 1C, the exposed oxide layer 16 at the opening 22 is further etched, by conventional photolithography and etching, so that the mask layer 18 is further exposed. Also, a portion of the oxide layer 20 uncovered by the photoresist layer 24 and a portion of the oxide layer 20 at the periphery of the opening 22 are etched to form an opening 26 and an opening 28, respectively, exposing the mask layer 18. The opening 28 further includes the opening 22.
Next, the photoresist layer 24 is removed by oxide plasma. A conductive layer 30 is formed by sputtering or CVD to fill the opening 22 and the opening 28 to contact with the conductive layer 14 and also to fill the opening 26.
Then, several continuous processes are performed to accomplish the dual damascene structure.
However, the conventional dual damascene technique requires more than two steps of photoresist coating and photolithography so that the processes are more complicate and misalignment tends to occur.